Silent Data Corruption (SDC) and No Trouble Found (NTF): Ways of Improving Test Towards 0 ppm

The identification and testing of semiconductor components is among the most expensive stages of memory production. Despite multi-insertion testing at several temperatures, customers still report application failures of 20–50 ppm for complex components such as dynamic random-access memory (DRAM), and field failures are often not reproducible in the production flow (no trouble found, NTF). This work examines whether application-based testing under application-representative conditions can expose such failures. Two platforms are used: an FPGA-based tester (RHINOE) with 192 sockets on six tiles, and an Intel CPU-based platform (OCTOPUS) that reproduces a customer memory-controller and BIOS environment. For about 10,000 4 G DDR3 devices, the conventional array test gave about 2% yield loss, whereas the FPGA-based application test gave about 6% at the same 98 °C/110 ms retention guard band. Five of ten customer-returned DDR3 devices, whose failures were not reproduced in the conventional flow, failed on the FPGA platform. In a 32-device cross-tile comparison, five devices that passed under calibrated settings failed when per-tile voltage calibration was omitted. In a one-week test of 1000 DDR4 devices, two transient single-cell events were observed. The results support application-based testing as a complement to production test; a zero-defect rate is not demonstrated, and the mechanisms of the transient events were not identified.