Self-Specializing Neuromorphic Computer: A Distributed Architecture Beyond the NPU

A concept paper proposing a self-specialising neuromorphic compute architecture built from existing technologies. Core ideas: Hardware that specialises itself through use: a RISC core offloading work to reconfigurable logic and analog memristor crossbars. Task training: specialisation through exposure to a varied class of related tasks, with checkpoints for rollback. Routing learned from results: inter-cell routes weighted by accuracy, speed and round-trip time, giving self-organisation and self-healing. Includes the motivation for departing from digital simulation of neural networks, related work, one illustrative implementation (component budget and power targets), and open questions for the community. Shared to stimulate discussion rather than as a finished design. Feedback welcome.