Multidimensional Bayesian Optimization of Nanosheet Double-Gate LDMOS for Enhanced Power Figure of Merit

Abstract This work investigates and optimizes a nanosheet-inspired Double-Gate Lateral Double-Diffused Metal-Oxide-Semiconductor (DG-LDMOS) architecture using Technology Computer-Aided Design (TCAD) simulations combined with Bayesian Optimization (BO), addressing the limitations of sequential manual tuning. By progressively expanding the optimization space from individual parameters to a six-dimensional design space, the optimized nanosheet DG-LDMOS intended for switched-mode operation achieves an intrinsic ultra-low specific on-state resistance of 0.17~m$\Omega\cdot$mm$^{2}$ and a breakdown voltage of 11.32~V, corresponding to a power figure of merit (FOM) of 738~kW/mm$^{2}$. The results reveal that FOM enhancement originates from coupled geometrical and doping optimization, which simultaneously shortens the conduction path, redistributes the lateral electric field, and enhances near-interface carrier transport. These findings demonstrate the importance of simultaneous optimization of strongly coupled device parameters and establish the nanosheet DG-LDMOS as a physics-based foundation for subsequent three-dimensional Gate-All-Around (GAA) LDMOS development.