ZnO–Te Anti-Ambipolar Switch Integration with Complementary Field-Effect Transistors Enabling a Pull-Middle Architecture for Standard Ternary Inverters

Abstract We demonstrate a pull-middle architecture for standard ternary inverters (STIs) operating at 77 K, enabled by the cointegration of a ZnO–Te antiambipolar switch (AAS) and vertically stacked ZnO/Te complementary field-effect transistors (CFETs) using a BEOL-compatible low-temperature process (≤150 °C). Operation at 77 K not only isolates the intrinsic pull-middle switching mechanism by suppressing thermally activated off-currents but also establishes the architecture’s immediate viability for extreme-environment computing, such as radiation-hardened space data centers and cryogenic aerospace systems. In this architecture, the ZnO–Te AAS acts as an independent pull-middle device connected to an explicit Vdd/2 node, while the ZnO and Te FETs in the CFET serve as the pull-down and pull-up devices, respectively. Unlike conventional ternary logic schemes governed by precise pull-up/pull-down current matching, by explicitly clamping the intermediate state, this architecture structurally prevents variation-induced voltage shifts and suppresses static power dissipation. Consequently, the proposed STI exhibits a narrow middle-state voltage distribution across 25 cells and achieves an I/O swing ratio of 1, with cascaded operation without level-restoring circuitry supported by measurement-calibrated circuit simulations. Ultimately, this vertically integrated ZnO/Te STI offers a compact and variation-tolerant platform for cryogenic logic, while presenting a material-optimization pathway toward room-temperature multivalued systems.