Physics-Constrained Thermal Influence Mode Superposition (3D-PIS) for Real-Time Volumetric Electro-Thermal Field Reconstruction in High-Density Electronics

Abstract Reliable thermal monitoring of high-density electronic assemblies is severely constrained by sparse on-board telemetry and the severe numerical stiffness of multi-material conjugate heat transfer. Conventional coordinate-based physics-informed neural networks (PINNs) that map continuous spatial coordinates (𝑥, 𝑦, 𝑧) →𝑇 encounter fundamental optimization barriers when resolving submillimeter, high-heat-flux active silicon dies embedded within orthotropic, low-conductivity FR-4 substrates. The resulting spatial discontinuities in thermal conductivity (∼ 3 orders of magnitude) cause catastrophic spectral bias and gradient vanishing. In this paper, we propose a 3D Physics- Constrained Thermal Influence Mode Superposition (3D-PIS) framework capable of reconstructing full volumetric temperature distributions from strictly 14 noisy surface sensors. A high-fidelity 380,800-cell (170 × 112 × 20) finite-volume method (FVM) benchmark is developed on an authentic single-board computer architecture containing an active SoC (3.6W), buck PMIC (1.8W), LPDDR4 memory (0.6W), and power inductors (0.6W), coupled through continuous internal copper planes, signal traces, and vertical thermal micro-vias. The proposed framework is comparatively benchmarked against classical empirical multiquadric Radial Basis Function (RBF) spatial interpolation and a continuous 3D coordinate-based PINN. While empirical RBF and coordinate PINNs suffer severe degradation (𝑅2 = 0.3210 and 𝑅2 = 0.2930, with localized peak errors exceeding 43 ◦C), the proposed 3D-PIS framework achieves a coefficient of determination 𝑅2 = 0.9331, an RMSE of 3.73 ◦C, and bounds maximum localized peak error to 17.54 ◦C across the entire 3D volume within 9.14 s on standard CPU hardware. These results demonstrate a robust, computationally tractable methodology for real-time digital twins in embedded edge computing and power electronics packaging.