ADAPTATION AND EVALUATION OF THE MEMBRAIN SYSTEM FOR PROFILE-GUIDED DATA PLACEMENT ON INTEL XEON MAX PROCESSORS

We investigate the efficient utilization of tiered HBM and DDR memory on Intel Xeon Max processors under constrained high-bandwidth memory capacity. Unlike conventional capacity-expansion architectures (DRAM + CXL/NVM), tiered memory management with an integrated HBM tier remains insufficiently explored. In this work, we adapt the MemBrain automated profile-guided data placement framework for Intel Xeon Max servers: implementing interprocedural allocation-site function cloning in the LLVM compiler, hardware monitoring of last-level cache misses via PEBS, and guided user-space memory placement via the Intel UMF library. We study data placement optimization strategies based on an exact combinatorial optimization model (knapsack problem) and heuristic selection algorithms. Experimental evaluation on the LULESH 2.0 and Graph500-BFS benchmarks demonstrates that profile-guided data placement achieves up to 98.4%–99.9% of pure HBM performance while utilizing only a fraction of its physical capacity.