A Topological Network Model for Wafer Map Defect Recognition Based on Persistent Homology Features and Bayesian Threshold Optimization

Wafer map defect recognition depends on shape, which makes persistent homology a natural representation, but existing topological treatments have been validated on synthetic maps whose defect rings are intact. We evaluate the representation on the real WM-811K benchmark under lot-disjoint evaluation. The novelty is threefold: a valid-die-mask filtration with an explicit, per-wafer stability constant, the use of that constant to turn threshold selection into a constrained problem, and a density-controlled test of which barcode summaries carry shape. The mask is necessary—a cubical complex on the raw array manufactures topology outside the wafer—and so is the choice of summary: total H1 persistence proxies the fraction of dies that failed and loses its association with the cyclic classes once that density is controlled for, whereas the dominant-loop share retains it. Those classes, Donut and Edge-Ring, are the only cyclic classes that WM-811K labels, and Donut spans only 233 lots, so this is a statement about them and not about cyclic defects in general. The die-flip stability bound we prove defines an admissible set of truncation levels, searched by Gaussian-process Bayesian optimization—a mechanism for solving that constrained problem, not a search strategy shown to beat random or grid search at equal budget. The guarantee is delimited: it governs which persistence bars survive truncation under a k-die perturbation, and covers neither the remaining feature coordinates nor any classifier’s predictions. Certified truncation costs 2.88 points of macro-F1 for the topological model [1.88,3.91] and 0.52 for the fusion model, whose interval includes zero. Fusing the two representations beats a capacity-matched convolutional model by 1.46 points with fewer parameters [0.78,2.18], and beats its own permutation control. Two design choices preceded the partition and enter only the topological branch, so these margins are upper estimates this design cannot correct. At 25 labeled wafers per class, the topological representation leads by 13.5 points [12.19,14.71]; by 400, the ordering has reversed. Lot-disjoint evaluation removes within-benchmark lot correlation; it does not establish transfer to another fab or acquisition process.