Design and performance analysis of optimized and unrolled Grain-80/128 stream ciphers on FPGA and ASIC platforms

Abstract Stream ciphers that are both lightweight and high-throughput are crucial for contemporary embedded, Internet of Things (IoT), and hardware designs with limited resources. Grain-80 and Grain-128 are two of the most popular solutions now in use because of their robust cryptographic capabilities and compact construction. However, for high-performance and real-time systems, conventional solutions are not adequate, because of their low throughput and significant initialization latency. In this work, we present optimized and unrolled hardware architectures of Grain-80 and Grain-128 stream ciphers for Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) platforms. The proposed designs are based on scalable unrolling techniques and architectural changes to improve throughput without sacrificing cryptographic accuracy. FPGA implementations on Spartan-6, Artix-7 and Virtex-7 devices show nearly linear throughput scaling, up to 10.67 Gbps for Grain-80 and 11.40 Gbps for Grain-128 at 16 $$X$$ unrolling on Virtex-7. The proposed architectures achieve single-cycle latency and increase the maximum operating frequency by more than 30% over conventional architectures. Significant improvements in energy efficiency are demonstrated by ASIC implementations generated with the Cadence Genus at 180 nm and normalized to 90 nm, 45 nm, and 28 nm technologies. At 180 nm, energy usage decreased from 2.005 pJ/bit to 1.267 pJ/bit for Grain-80 and from 2.210 pJ/bit to 1.978 pJ/bit for Grain-128. These findings demonstrate that the suggested architectures are appropriate for both lightweight and high-performance cryptographic tasks since they provide a balanced trade-off between throughput, latency, area, and energy savings.