The Adiabatic Optimum: Where Leakage Ends the 1/T Law in Slow-Charging Logic

Adiabatic (charge-recovery) logic promises dissipation falling as 1/T as switching slows, but leakage does not fall, so the total energy per operation E(T) = K/T + P_leak T has a minimum at a finite switching time. For a stated device model built from published parameters (loaded gate C = 1 fF at 0.75 V, RC = 10 ps, power-clock efficiency 0.80, baseline leakage 1 nA per gate, 0.75 nW, at 300 K) the optimum is T* = 3.06 ns (327 MHz) with minimum energy 4.59e-18 J per operation, a factor of 61.24 below conventional switching at the same node (conventional figure from the companion switching-reliability calculation). At the optimum an adiabatic machine delivers 2.18e17 operations per second per watt, 61.29 times the conventional figure, but a sequential chain runs 9.19 times slower than a 3 GHz conventional gate. Over a leakage range of 0.01 to 100 times baseline the advantage falls from a factor of 612 to 6.12, and at 360 K it is 7.65. Charge recovery suits throughput-oriented, latency-tolerant computation on cool, low-leakage processes. Model calculations are labelled SIMULATED, NOT MEASURED. The deposit includes the paper PDF, the computation script (compute.py) that produces every number in the paper, and its outputs (results.json, results.txt).