FPGA-Based Design and Verification of a Hazard-Aware Pipelined RISC-V Processor with an Optimized APB Interface for Ethernet Applications

The increasing demand for high-performance and energy-efficient embedded systems has increased the adoption of open-source RISC-V processor architectures for communication and system-on-chip applications. However, pipelined processor architectures are vulnerable to data hazards, which can reduce execution performance and affect system reliability if not efficiently handled. Further, efficient communication between the processor and peripheral interfaces is required for latency-sensitive applications such as Ethernet communication. This work presents a hazard-aware pipelined RISC-V processor design and verification on FPGA with an integrated Optimized Advanced Peripheral Bus (OptiAPB) interface for Ethernet applications. The proposed processor has an efficient data hazard detection mechanism for instruction dependencies and appropriate pipeline control to improve the instruction execution reliability. To improve pipeline efficiency, a mechanism for detecting data hazards and single-cycle stall insertion as well as data-forwarding paths from the EX/MEM and MEM/WB stages to the execute stage are incorporated. The branch instructions are resolved by target address calculation in the execute stage with a two-cycle pipeline flush mechanism. The OptiAPB interface is designed to provide efficient processor-to-peripheral communication by minimizing transfer latency and implementation overhead. The processor is integrated into a system-on-chip architecture comprising the CPU, instruction decoder, 256-word memory, bus interface, memory-mapped APB register interface, and an Ethernet MAC controller. The Ethernet subsystem incorporates finite-state-machine-based transmit and receive modules, a hardware CRC32 engine, and 16-entry transmit and receive FIFO buffers to support reliable frame communication. The complete design is implemented on a Xilinx Artix-7 XC7A100T FPGA and utilizes 658 LUTs, 349 slice registers, no BRAM or DSP blocks, and 20 bonded I/O pins with memory implemented using distributed RAM. The proposed processor achieves a maximum operating frequency of 158.74 MHz with a CPI of 1.30, an IPC of 0.77, and an execution performance of 112.39 MIPS. We evaluate the proposed framework by comparing it to recent state-of-the-art implementations to show its effectiveness. Our results show that the proposed design achieves 100% FSM coverage, while the existing implementations have reported coverage values ranging from 90.12% to 94.44%. Moreover, the comparative evaluation highlights the efficiency of the proposed architectural enhancements in terms of processor throughput improvement, timing closure and overall FPGA implementation performance. These results confirm the usefulness of the presented framework for efficient and reliable FPGA-based processor and communication applications.