HARDWARE INTEGRATION OF NFNS AND SBNS NUMERAL SYSTEMS IN A FAULT-TOLERANT NEUROMORPHIC PROCESSOR ARCHITECTURE

This paper investigates the microarchitectural principles and technological prospects of designing a fundamentally new class of computing devices – a hybrid fault-tolerant neuromorphic processor. The feasibility of deep hardware integration of the New Fibonacci Numeral System (NFNS) and the Scaled Bergman Numeral System (SBNS) on a single semiconductor die is substantiated. It is demonstrated that due to the identical nature of their underlying mathematical principles (representation of weights via fractions, Fibonacci confluent/convoluted rules), both systems can share up to 85–90% of the physical area of the arithmetic logic unit (ALU) and utilize a unified hardware parity filter. A mechanism for dynamic on-the-fly switching of the computational basis within a single clock cycle via a configuration register depending on the specific application task is described. A technological forecast is formulated, according to which the integer NFNS mode ensures noise immunity and error control (bit-flips) in critical discrete environments (aerospace, cryptography), while the SBNS mode, leveraging the Truncation Symmetry Theorem, eliminates the accumulation of rounding errors and optimizes the bit-width of the significant register mantissa, serving as an ideal foundation for neuromorphic AI accelerators.