Design and implementation of a high-speed reversible arithmetic logic unit for power-efficient computing

Abstract This paper presents the design, simulation, and hardware validation of a high-speed, power-efficient reversible Arithmetic Logic Unit (ALU) architecture, implemented in Verilog HDL. The ALU consists of three modular blocks—Arithmetic, Logical, and Control Units—and employs reversible logic gates to minimize power consumption and information loss. The proposed design achieves a Total Reversible Logic Instruction Count (TRLIC) of 53, reflecting a 62.67% improvement over prior works. Functional verification was carried out through simulation in Xilinx Vivado and ISE 14.7, followed by FPGA prototyping on the NEXYS A7 (Artix-7) board, confirming accurate operation. Beyond FPGA validation, the design was synthesized and implemented as an ASIC using Cadence Genus and Innovus with the 90-nm CMOS technology, completing the RTL-to-GDSII physical-design flow. The ASIC implementation achieved a critical-path delay of 1.195 ns, with a reported switching power of 1.72 µW.