The Energy Cost of Clock Distribution: Practice, a Thermal-Noise Floor, and the Gap Between Them

The clock network of a synchronous processor carries no information other than timing, yet reported figures attribute between one fifth and one half of total chip power to it. For the Intel Core i9-14900K at 253 W maximum turbo power and 5.6 GHz, the central literature fraction of 0.30 assigns 75.9 W to clocking, or 13.55 nJ per cycle. A thermal-noise floor is derived for distributing a timing edge at a stated rms timing tolerance: at 5 ps and 350 K the floor is 1.21e-19 J per receiving node per cycle (25 kT), so practice sits about 5.6e3 (3.7 orders of magnitude) above the floor per node. A wire-capacitance H-tree model shows the global distribution tree is a minority of clock energy; most of the cost is local. Clock gating and multiple clock domains recover substantial but bounded, overlapping shares. Model calculations are SIMULATED, NOT MEASURED. The computation script and its full results are included and produce every number in the paper.