An ISA-Centric RISC-V Heterogeneous Architecture for Energy Efficient Ray Tracing Pipeline Acceleration

Ray tracing (RT) is increasingly used in interactive graphics and edge rendering, but efficient deployment remains difficult because its two major phases, BVH construction and BVH traversal, have fundamentally different computation patterns, precision requirements, and architectural affinities. Existing designs largely optimize these phases in isolation and therefore do not provide an efficient full-pipeline solution. We present an ISA-centric RISC-V heterogeneous architecture for energy-efficient RT acceleration through phase-aware hardware-software co-design. The design has three components: a full-BVH compression framework that combines exact lossless compression for leaf-triangle blocks with conservative multi-level quantization for AABBs and rays; custom RISC-V ISA extensions for both vectorized BVH-construction kernels and correctness-preserving low-precision traversal; and a phase-aware heterogeneous organization that couples a RVV-enhanced core for construction with a precision-aware traversal coprocessor. For BVH construction, our design achieves speedups of 2.38 × and 1.97 × over XT910 with RVV for SAH-2 and LBVH-2. Compared with Jetson AGX Orin across different BVH widths (BVH2/4/6/8), our design achieves up to 1.59× and 1.77× speedups for SAH and LBVH, while consuming only 20.53%–32.46% of its energy. For BVH traversal, it achieves 1.42 × speedup over AQB8, while consuming only 31.79% of AQB8’s energy. Across different BVH widths, our design achieves up to 2.50× and 2.64× speedups for SAH and LBVH over Orin, while consuming only 27.19%–51.02% of its energy. These results demonstrate that phase-aware ISA-centric design enables efficient, programmable full-pipeline ray tracing.