Balancing Performance and Energy Efficiency: A Comparative Review of Near-Data Processing, Heterogeneous Cores, Persistent Memory Controllers, and Chiplet-Based Disaggregated Memory

Computers keep getting faster, but moving data between memory and the processor can now cost more time and energy than the computation itself. This paper presents a comparative review of four architectural directions that try to deal with this problem: near-data processing (NDP), heterogeneous core integration, persistent memory controllers, and chiplet-based disaggregated memory. NDP moves part of the work to where the data already sits, so fewer transfers are needed. Heterogeneous processors mix fast cores with frugal ones and give each task to whichever suits it better. Persistent memory controllers manage memory that keeps its contents without power, so they have to balance durability, write endurance, and latency. Chiplet and disaggregated designs break a system into smaller pieces that can be scaled separately, but they bring interconnect delays, coherence problems, and harder software management. Recent survey literature was reviewed and compared in terms of performance, energy efficiency, scalability, reliability, programmability, and cost. The review finds that no single approach wins on every workload. NDP fits data-heavy tasks built from simple operations, heterogeneous cores fit mixed workloads, persistent memory fits applications that need durable state, and chiplets fit systems that have to grow in flexible ways. The most promising path is to combine them through coordinated hardware and software design and to measure energy at the whole-system level. Gaps remain in shared benchmarks, workload-aware scheduling, and cross-layer evaluation.

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Publication Details

Journal
Zenodo (CERN European Organization for Nuclear Research)
Published
2026-11-09
DOI
https://doi.org/10.5281/zenodo.24079811
Primary Topic
Parallel Computing and Optimization Techniques
Type
article
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article

Balancing Performance and Energy Efficiency: A Comparative Review of Near-Data Processing, Heterogeneous Cores, Persistent Memory Controllers, and Chiplet-Based Disaggregated Memory

Jay Ar P. Esparcia, Dan Michael C. Carajay, Andrea Rose N. Diaz
Zenodo (CERN European Organization for Nuclear Research)
Parallel Computing and Optimization Techniques
article

Balancing Performance and Energy Efficiency: A Comparative Review of Near-Data Processing, Heterogeneous Cores, Persistent Memory Controllers, and Chiplet-Based Disaggregated Memory

Jay Ar P. Esparcia, Dan Michael C. Carajay, Andrea Rose N. Diaz
article en

Abstract

Computers keep getting faster, but moving data between memory and the processor can now cost more time and energy than the computation itself. This paper presents a comparative review of four architectural directions that try to deal with this problem: near-data processing (NDP), heterogeneous core integration, persistent memory controllers, and chiplet-based disaggregated memory. NDP moves part of the work to where the data already sits, so fewer transfers are needed. Heterogeneous processors mix fast cores with frugal ones and give each task to whichever suits it better. Persistent memory controllers manage memory that keeps its contents without power, so they have to balance durability, write endurance, and latency. Chiplet and disaggregated designs break a system into smaller pieces that can be scaled separately, but they bring interconnect delays, coherence problems, and harder software management. Recent survey literature was reviewed and compared in terms of performance, energy efficiency, scalability, reliability, programmability, and cost. The review finds that no single approach wins on every workload. NDP fits data-heavy tasks built from simple operations, heterogeneous cores fit mixed workloads, persistent memory fits applications that need durable state, and chiplets fit systems that have to grow in flexible ways. The most promising path is to combine them through coordinated hardware and software design and to measure energy at the whole-system level. Gaps remain in shared benchmarks, workload-aware scheduling, and cross-layer evaluation.

Zenodo (CERN European Organization for Nuclear Research)
University of Southern Mindanao (PH)
Parallel Computing and Optimization Techniques
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Balancing Performance and Energy Efficiency: A Comparative Review of Near-Data Processing, Heterogeneous Cores, Persistent Memory Controllers, and Chiplet-Based Disaggregated Memory — Jay Ar P. Esparcia, Dan Michael C. Carajay, et al. · Zenodo (CERN European Organization for Nuclear Research) (2026) | TGRS Research Map | TGRS