Soft-error tolerant design and assessment of the system-on-chip circuit for space application

As semiconductor technology advances, System-on-Chip (SoC) devices have become increasingly vulnerable to space radiation, leading to a higher incidence of soft errors. This paper presents a comprehensive soft-error tolerant design for an SoC. The SoC core is hardened against soft errors through pipeline recovery. The cache subsystem features multi-level novel soft-error protection. The bus matrix is equipped with interfaces capable of correcting single-bit and adjacent double-bit errors. On-chip SRAM resilience is improved using an effective four-bit burst-error-correcting code combined with autonomous detection and write-back mechanisms to prevent error accumulation. A fault injection platform is developed to assess the soft-error tolerance and its validation. The assessment results show a significant reduction in error rates from over 50% to below 25%. In this work, the overheads such as frequency, area and power consumption are compared and analysed through the implementation of a 65 nm CMOS process. The soft-error rate of the rad-hard SoC is approximately 4.57 × 10−8 error/device•day for GEO orbit by heavy-ion experiments. It is indicated that the multiple soft-error tolerance methods described in this paper are effective for SoC circuits.