Bit-Level Verification of Membrane Potential and Spikes in a Fixed-Point LIF Neuron and a 256-Neuron Spiking Network

Abstract Spiking neuron models are small enough to run on inexpensive FPGAs, but a hardware result is only useful for model-based experiments if one can state exactly how it differs from the model. We present a leaky integrate-and-fire (LIF) neuron and a 256-neuron network on a low-cost FPGA (Tang Nano 20K, Gowin GW2AR-18), and we test both against a Python reference model. The model uses signed Q8.8 fixed-point state, saturating additions and shift-based time constants, so no multiplier is needed. On the board, the single neuron’s membrane potential and spike matched the model at every step of 60,000 samples from three hand-picked parameter sets and of 2,023,200 samples from a sweep of 2,248 parameter sets, all with constant input currents. The synaptic current was not read back, so it is not compared directly. A time-multiplexed network with spike-driven synapses, controlled over a UARTlink, matched the model in every reply of a 682-frame command flow, and in the spike counts, the final-state snapshot and the first 512 steps of spikes of five excitation/inhibition (E/I) conditions. Spike timing after step 512 was not compared, and the membrane potential of the network only at the last step. Mutation tests show that the checkers can fail. The full design uses 12% of the logic and 98% of the block RAM, and meets timing at 38.75 MHz after place and route, against a 27 MHz clock. In the model, the mean firing rate of the network falls monotonically as the inhibitory fraction rises, in all 240 networks of the sweep; at low inhibition the rate is limited by the refractory ceiling. On the board, the current reached its upper and lower limits and the potential its lower limit, and every saturated step matched the model, including a negative threshold where the lower limit decides a spike; the upper limit of the potential cannot change the output. The membrane potential of the network was compared only at the last step, so saturation inside the network was not checked. We also report the limits we found: a USB–UART link that lost bytes in long unpaced bursts, a command decoder without a time-out, and a spike trace that covers only the first 512 steps. The hardware is validated against the model only; we make no claim about biological validity.

Authors

Institutions

Publication Details

Journal
Research Square
Published
2026-11-09
DOI
https://doi.org/10.21203/rs.3.rs-11650337/v1
Primary Topic
Advanced Memory and Neural Computing
Type
preprint
Controls
|||
ALL TIME
JAN
FEB
MAR
APR
MAY
JUN
JUL
AUG
SEP
OCT
NOV
preprint

Bit-Level Verification of Membrane Potential and Spikes in a Fixed-Point LIF Neuron and a 256-Neuron Spiking Network

ChiaAn Lin
Research Square
Advanced Memory and Neural Computing
preprint

Bit-Level Verification of Membrane Potential and Spikes in a Fixed-Point LIF Neuron and a 256-Neuron Spiking Network

ChiaAn Lin
preprint en

Abstract

Abstract Spiking neuron models are small enough to run on inexpensive FPGAs, but a hardware result is only useful for model-based experiments if one can state exactly how it differs from the model. We present a leaky integrate-and-fire (LIF) neuron and a 256-neuron network on a low-cost FPGA (Tang Nano 20K, Gowin GW2AR-18), and we test both against a Python reference model. The model uses signed Q8.8 fixed-point state, saturating additions and shift-based time constants, so no multiplier is needed. On the board, the single neuron’s membrane potential and spike matched the model at every step of 60,000 samples from three hand-picked parameter sets and of 2,023,200 samples from a sweep of 2,248 parameter sets, all with constant input currents. The synaptic current was not read back, so it is not compared directly. A time-multiplexed network with spike-driven synapses, controlled over a UARTlink, matched the model in every reply of a 682-frame command flow, and in the spike counts, the final-state snapshot and the first 512 steps of spikes of five excitation/inhibition (E/I) conditions. Spike timing after step 512 was not compared, and the membrane potential of the network only at the last step. Mutation tests show that the checkers can fail. The full design uses 12% of the logic and 98% of the block RAM, and meets timing at 38.75 MHz after place and route, against a 27 MHz clock. In the model, the mean firing rate of the network falls monotonically as the inhibitory fraction rises, in all 240 networks of the sweep; at low inhibition the rate is limited by the refractory ceiling. On the board, the current reached its upper and lower limits and the potential its lower limit, and every saturated step matched the model, including a negative threshold where the lower limit decides a spike; the upper limit of the potential cannot change the output. The membrane potential of the network was compared only at the last step, so saturation inside the network was not checked. We also report the limits we found: a USB–UART link that lost bytes in long unpaced bursts, a command decoder without a time-out, and a spike trace that covers only the first 512 steps. The hardware is validated against the model only; we make no claim about biological validity.

Research Square
National Taiwan University (TW)
Advanced Memory and Neural Computing
AI Navigator

Ask Laika to Summarize, Analyze, and Connect papers live on the map.

Summarize Papers & Methodologies

Extract key findings, datasets, and comparative methods across publications.

Benchmark Rankings & Visual Analytics

Rank top research institutions, authors, funders, topics, and journals by Field-Weighted Citation Impact (FWCI) and paper volume with instant charts.

Connect Distant Disciplines

Bridge topological clusters on the map to find hidden collaborative intersections.

Laika access coming soon