The Expanding Battlefield of Microarchitectural Vulnerabilities: A Survey on Defining and Reducing the Timing Side-Channel Attack Surface through Vulnerability Assessment and Simulation

Novel Microarchitectural Timing-based Side Channel Attacks (MTSCAs) are being discovered each year, taking advantage of performance features in microarchitectures. The increasingly complex System-on-Chip (SoC) designs, the wide range of customer-available CPUs, and the rise of RISC-V are creating an ever-expanding attack surface for MTSCAs, making the detection and mitigation of MTSCAs fall short compared to the rate of newly discovered attacks. To reduce the attack surface, we recommend prioritizing the identification and analysis of the underlying vulnerabilities with the help of vulnerability assessment and simulation tools. In this work, we provide a comprehensive survey of MTSCAs, with a focus on the exploited vulnerabilities underneath. Then, we define and evaluate the attack surface of currently available architectures, and highlight the challenges to reduce it. We demonstrate that vulnerability assessment is fundamental for this objective and propose an overview of the existing techniques and frameworks available, along with their respective attack surface coverage. Finally, we identify simulation as a key direction for vulnerability assessment and highlight how gem5 simulation can provide valuable insight into attacks in order, enabling more effective vulnerability analysis.