A High-Throughput DSP-Free PRNG for FPGA based on Xoshiro128** and Integer Chaotic Mixing

Abstract This paper presents a resource-conscious hybrid pseudo-random number generator (PRNG) core implemented in an out-of-context (OOC) flow on the Xilinx Zynq-7000 SoC platform. The proposed architecture combines a Xoshiro128** state engine with a Weyl sequence and a discretized integer Tent map to provide near-uniform output statistics while maintaining low resource usage. The design uses branchless integer arithmetic only and does not require digital signal processing (DSP) slices or Block RAM. The fully pipelined implementation achieves an initiation interval of 1 and sustains a throughput of 5.82 Gbps at 181.82 MHz. Post-implementation results on a Zynq xa7z010 device show a footprint of 939 slice LUTs, 1071 registers, and a dynamic power consumption of 29 mW. The generator passes the NIST SP 800-22, Dieharder, and TestU01 BigCrush test suites in the reported evaluation, and exhibits near-uniform output statistics and measurable sensitivity to changes in the initialization state. The six active 32-bit initialization parameters define a nominal 192-bit initialization-input space. These results suggest that the proposed design may be suitable for resource-constrained embedded applications. The proposed scheme achieves better performance than recent architectures in various aspects.