Design of an X-Band 50-W, 12-Way GaN HEMT Power Amplifier Using an Integrated FET Process

This paper presents the design, fabrication, and measurement of a 50W-class GaN HEMT power amplifier for X-band radar and satellite communication systems. To overcome single-device output limitations and achieve high integration, a 12-way parallel combining structure based on an Integrated FET process was proposed. The amplifier features integrated 4-way and 12-way divider/combiner stages within the chip to minimize loss. Phase and amplitude imbalances were resolved, achieving <0.4 dB amplitude error and <1° phase error. Alumina and Taconic RF-35 substrates were used for the RF and bias circuits, respectively, to ensure stable DC supply and high isolation. Evaluated at 10 GHz with a 25 us pulse width and 10% duty cycle, the fabricated amplifier demonstrated 47.78 dBm (approx. 60 W) output power, 44.11% PAE, 16.72 dB small-signal gain, and 12.76 dB large-signal gain, satisfying all design goals. This topology is applicable to next-generation high-power RF systems.

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Publication Details

Journal
The Transactions of The Korean Institute of Electrical Engineers
Published
2026-11-09
DOI
https://doi.org/10.5370/kiee.2026.75.11.2930
Primary Topic
Advanced Power Amplifier Design
Type
article
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article

Design of an X-Band 50-W, 12-Way GaN HEMT Power Amplifier Using an Integrated FET Process

Dal Ahn, Kwanhun Jeong, Jongsik Lim, Tae-Hwan Jeong et al.
The Transactions of The Korean Institute of Electrical Engineers
Advanced Power Amplifier Design
article

Design of an X-Band 50-W, 12-Way GaN HEMT Power Amplifier Using an Integrated FET Process

Dal Ahn, Kwanhun Jeong, Jongsik Lim, Tae-Hwan Jeong, You-Na Jang, Dong-Hoon Kang, Insup Kim, Yeon-Su Kim
article en

Abstract

This paper presents the design, fabrication, and measurement of a 50W-class GaN HEMT power amplifier for X-band radar and satellite communication systems. To overcome single-device output limitations and achieve high integration, a 12-way parallel combining structure based on an Integrated FET process was proposed. The amplifier features integrated 4-way and 12-way divider/combiner stages within the chip to minimize loss. Phase and amplitude imbalances were resolved, achieving <0.4 dB amplitude error and <1° phase error. Alumina and Taconic RF-35 substrates were used for the RF and bias circuits, respectively, to ensure stable DC supply and high isolation. Evaluated at 10 GHz with a 25 us pulse width and 10% duty cycle, the fabricated amplifier demonstrated 47.78 dBm (approx. 60 W) output power, 44.11% PAE, 16.72 dB small-signal gain, and 12.76 dB large-signal gain, satisfying all design goals. This topology is applicable to next-generation high-power RF systems.

The Transactions of The Korean Institute of Electrical EngineersVol. 75(11)
Advanced Power Amplifier Design
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