The Spark Secrets: What I Did to the NVIDIA CUDA Stack on the DGX Spark

On November 7, 2026, GitHub flagged my organization aien-dev, hid it from the public, and suspended my aien-spark account, citing a violation of its Terms of Service and naming no clause, no act, and no content. This document publishes, on infrastructure GitHub does not control, the findings that platform hosted: how I replaced the CUDA user-space stack on my NVIDIA DGX Spark (Grace Blackwell GB10, sm_121). Contents: the driver-client sequence that performs everything libcuda performs, written against NVIDIA's own published open kernel module headers (about 900 lines; object classes, UVM registration, GPFIFO channel construction); kernel submission as an 8-byte ring entry plus a single 32-bit doorbell store, with no system call on the path; the GPU-uncached polling rule; the QMD launch descriptor built directly, with dependent launch cost measured at 24 to 31 microseconds; the recovery of the undocumented sm_121 SASS machine-code encoding by probe differencing, Mesa NAK records, and on-chip arithmetic fitting (59 instruction kinds, golden words in tests); the shared timing-word encoder bug and its fix; numerics closed on the chip over the entire 2^32 input domain (reductions, eleven transcendental functions, zero mismatches); probe-measured ceilings of 115.14 TFLOPS tensor peak and 195.1 GB/s memory reads on one GB10; a 35-billion-parameter model served with zero CUDA libraries in the process, proven from the process map; the attention-kernel measurements for the Qwen3.8-27B shape; and a model trained on the GB10 in my own Omega language with no CUDA runtime (15.8M parameters, 0.449322 bits per byte held-out at step 60,000). Limits, printed in the document and kept here: NVIDIA's open kernel module still sits in the serving path; my replacement GB10 driver is source and simulator gates only and has never been loaded on hardware; the GSP firmware remains NVIDIA's; my own disassembler is unfinished; a public qualification queue lists the rest; every figure comes from one GB10 in one machine. The full method and receipts live in the CUDA++ toolchain (aien-dev/CUDApp) and the Omega repository (aien-dev/omega-mv), in migration to Radicle. Full paper: Reverse Engineering the CUDA Software Stack (DOI 10.5281/zenodo.23578453).

Authors

Publication Details

Journal
Zenodo (CERN European Organization for Nuclear Research)
Published
2026-11-07
DOI
https://doi.org/10.5281/zenodo.24032442
Primary Topic
Parallel Computing and Optimization Techniques
Type
preprint
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preprint

The Spark Secrets: What I Did to the NVIDIA CUDA Stack on the DGX Spark

Drake Stapleton
Zenodo (CERN European Organization for Nuclear Research)
Parallel Computing and Optimization Techniques
preprint

The Spark Secrets: What I Did to the NVIDIA CUDA Stack on the DGX Spark

Drake Stapleton
preprint en

Abstract

On November 7, 2026, GitHub flagged my organization aien-dev, hid it from the public, and suspended my aien-spark account, citing a violation of its Terms of Service and naming no clause, no act, and no content. This document publishes, on infrastructure GitHub does not control, the findings that platform hosted: how I replaced the CUDA user-space stack on my NVIDIA DGX Spark (Grace Blackwell GB10, sm_121). Contents: the driver-client sequence that performs everything libcuda performs, written against NVIDIA's own published open kernel module headers (about 900 lines; object classes, UVM registration, GPFIFO channel construction); kernel submission as an 8-byte ring entry plus a single 32-bit doorbell store, with no system call on the path; the GPU-uncached polling rule; the QMD launch descriptor built directly, with dependent launch cost measured at 24 to 31 microseconds; the recovery of the undocumented sm_121 SASS machine-code encoding by probe differencing, Mesa NAK records, and on-chip arithmetic fitting (59 instruction kinds, golden words in tests); the shared timing-word encoder bug and its fix; numerics closed on the chip over the entire 2^32 input domain (reductions, eleven transcendental functions, zero mismatches); probe-measured ceilings of 115.14 TFLOPS tensor peak and 195.1 GB/s memory reads on one GB10; a 35-billion-parameter model served with zero CUDA libraries in the process, proven from the process map; the attention-kernel measurements for the Qwen3.8-27B shape; and a model trained on the GB10 in my own Omega language with no CUDA runtime (15.8M parameters, 0.449322 bits per byte held-out at step 60,000). Limits, printed in the document and kept here: NVIDIA's open kernel module still sits in the serving path; my replacement GB10 driver is source and simulator gates only and has never been loaded on hardware; the GSP firmware remains NVIDIA's; my own disassembler is unfinished; a public qualification queue lists the rest; every figure comes from one GB10 in one machine. The full method and receipts live in the CUDA++ toolchain (aien-dev/CUDApp) and the Omega repository (aien-dev/omega-mv), in migration to Radicle. Full paper: Reverse Engineering the CUDA Software Stack (DOI 10.5281/zenodo.23578453).

Zenodo (CERN European Organization for Nuclear Research)
Parallel Computing and Optimization Techniques
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