Bias-History-Driven Negative Differential Resistance in Heterojunction-Free WSe2 Multilayers

Abstract As conventional complementary metal–oxide–semiconductor technology approaches its fundamental scaling limits in binary logic, alternative device concepts have attracted increasing attention. Negative differential resistance (NDR) devices offer a promising route toward multivalued logic. However, their practical implementation requires both a high peak-to-valley current ratio (PVCR) and high drive current density at room temperature, necessitating complex device architectures and fabrication processes. Here, we report a heterojunction-free WSe2 NDR device on a hexagonal boron nitride dielectric, exhibiting a PVCR of up to 42.9 and a width-normalized peak current density of approximately 280.8 μA/μm at room temperature. The NDR emerges evidently after gate-polarity reversal, thus suggesting the formation of a bias-history-dependent nonequilibrium carrier configuration. Systematic variations of the gate-bias magnitude, duration, hold time, and sweep rate indicate that the relaxation of this nonequilibrium carrier configuration governs the peak current, peak voltage, and PVCR of the NDR characteristics. Surface passivation using poly(methyl methacrylate) further enhances both the PVCR and peak current, highlighting the sensitivity of the NDR to the surface electrostatic environment. These findings establish a bias-history-driven electrostatic mechanism for NDR in homogeneous two-dimensional layered semiconductors and provide a simple and scalable strategy for realizing high-performance heterojunction-free NDR devices.