An Efficient Approximate Multiplier for Error-Resilient Neural Network and Image Processing Applications

Approximate computing has emerged as a viable paradigm to balance accuracy and hardware efficiency, as the demand for edge computing increases. While multipliers are inherently powerintensive components, their approximation can lead to significant power savings. Although approximate compressors are effective for unsigned arithmetic, they often result in substantial accuracy degradation in signed multipliers. To mitigate this issue, a multiplier was developed to optimally utilize approximate compressors. Additionally, two novel approximate 4-2 compressors are introduced. The error metrics of the proposed multiplier were compared with state-of-the-art designs, and all hardware designs were synthesized and implemented using Cadence Innovus with a 90 nm ASIC technology node. The hybrid utilization of the two proposed compressors in the designed multiplier achieved reductions of 39.26% in area, 49% in power, 18.63% in delay, and 74.8% in the power-delay area product (PDAP) compared to the exact Baugh-Wooley multiplier. The efficacy of the proposed multiplier was validated using neural network inference and Sobel edge detection. The results indicated that the proposed multiplier maintains the baseline accuracy, with only a 0.06% deviation in classification accuracy for Multilayer Perceptron (MLP) and a 0.14% deviation for ResNet-50, and no discernible deterioration in edge-detection quality.