Optimization of Montgomery Multiplication via MATLAB HDL Coder for FPGA Implementation

Abstract Field-Programmable Gate Arrays (FPGAs) are essential for implementing and verifying complex computational algorithms. This paper is part of a series of research aimed at enabling developers to use FPGAs as an embedded system without prior knowledge of digital design engineering. This paper discusses minimizing combinatorial delay that exists in complex algorithm computation using a software pipeline. How to implement this pipeline using a MATLAB HDL Coder algorithm. A comparison of the implementation of the complex Montgomery Multiplication Algorithm, with and without a pipeline, is performed on the same Virtex-7 platform. The Experiment shows a 56.5\% improvement in the maximum frequency, 128.810 MHz. Although the utilization of slice registers increased by 1\%, the number of slice-LUTs increased by 13\%, the number of fully used LUT-FF pairs increased by 7\%, and memory usage remained constant, demonstrating that high-level optimizations can produce hardware performance that typically requires expert-level manual RTL design.