Posterior-Mean Conversion of a Variational Bayesian Neural Network for Fixed-Point RTL Evaluation: An MNIST Case Study

Abstract Bayesian neural networks represent model parameters using probability distributions and can provide information about parameter and predictive uncertainty. However, the sampling operations associated with Bayesian inference can increase computational and hardware requirements, in resource-constrained embedded systems. This work investigates an implementation-oriented workflow for converting a Bayesian-trained neural network into a deterministic fixed-point representation for FPGA-oriented evaluation. A BNN was trained on the MNIST handwritten-digit dataset using variational inference. Following training, the posterior means of the learned parameters were extracted to construct a deterministic approximation, thereby removing stochastic parameter sampling during inference. The resulting deterministic model was quantized using QKeras with a 10-bit fixed-point representation and evaluated in software. A separate fixed-point representation of the deterministic model was used to generate a custom Verilog-oriented implementation for RTL verification and FPGA-oriented analysis. The Bayesian neural network achieved a classification accuracy of 94.01\% on the complete MNIST test dataset using 30 Monte Carlo samples, while the posterior-mean deterministic model achieved 93.98\%. The 10-bit quantized software model achieved 93.87\% on the same test dataset. The available synthesis results reported 2,474 lookup tables, 2,201 flip-flops, and 141 DSP resources. The reported power consumption of 1.665 W was obtained through Vivado power estimation and therefore represents a tool-based estimate rather than a direct board-level measurement. Hardware-oriented validation was limited to directed test vectors and was used to verify the functional operation of the RTL implementation rather than to establish complete test-set accuracy. The results demonstrate the feasibility of converting a variationally trained Bayesian neural network into a deterministic and quantized FPGA-oriented representation. However, explicit uncertainty estimation is not retained after posterior-mean conversion, and complete hardware test-set accuracy, measured latency, and board-level power consumption were not established. The study therefore presents an implementation-oriented feasibility case study rather than a new Bayesian inference algorithm or FPGA architecture.