WISHBONE 32-bit: The FPGA-SoC System Bus and Its Implementation on Tang Nano 20K

Wishbone is an open specification for synchronous IP-core interconnection insystems-on-chip. On our Tang Nano 20K, the factory LiteX BIOS reports “BUS: WISHBONE 32-bit @4GiB”. This paper explains the meaning of that line, the mechanics of request/acknowledgementtransfers, the performance impact of waiting for ACK, and why a 4 GiB address space is not equivalentto 4 GiB of installed RAM. It provides illustrative timing, a compact Verilog peripheral and areproducible experimental plan