Resilience of Sub-10 nm MoSi2N4 and WSi2N4 TFETs Against Surface Roughness: Device and Digital Applications

Abstract Monolayers of the \((\mathrm{MA}_2\mathrm{Z}_4)\) family, particularly \((\mathrm{MoSi}_2\mathrm{N}_4)\) and \((\mathrm{WSi}_2\mathrm{N}_4)\), are promising channel materials for steep-slope tunnel field-effect transistors (TFETs) in beyond-CMOS electronics. However, interface imperfections introduce critical device variability. Here, we investigate the impact of substrate surface roughness on sub-10 nm \((\mathrm{MoSi}_2\mathrm{N}_4)\) and \((\mathrm{WSi}_2\mathrm{N}_4)\) TFETs using a tight-binding model within the non-equilibrium Green's function (NEGF) formalism. The surface corrugation induces localized midgap states, triggering parasitic trap-assisted tunneling that elevates the OFF-current and degrades the sub-threshold swing. Although both 2D channels show strong resilience up to an RMS roughness of \((\delta h \approx 150)\)pm-maintaining intrinsic delays as fast as \((\tau \approx 0.20\text{--}0.25)\) ps at \((L_\mathrm{ch} = 3)\) nm-higher roughness severely suppresses the ON-current and compresses the ON-OFF current ratio by four orders of magnitude. Monolayer \((\mathrm{WSi}_2\mathrm{N}_4)\) consistently demonstrates superior electrostatic robustness compared to \((\mathrm{MoSi}_2\mathrm{N}_4)\). Furthermore, inverter simulations reveal degraded transition slope with surface roughness. These results emphasize the need for atomically smooth substrates or planarization techniques to preserve steep-slope switching in scaled 2D nanoelectronics.