VexRiscv: A Configurable RISC-V Architecture and VexRiscv_Min on Tang Nano 20K

This article presents the organization of VexRiscv, a configurable 32-bit RISC-V core, itshardware generation with SpinalHDL, pipeline and interface options, memory-subsystem configurationsand integration with LiteX. A separate case study examines the operational factory SoC on a Sipeed TangNano 20K through its UART boot log. Direct observations, claims supported by project sources, andproperties requiring further verification are kept distinct.