Hardware-Aware On-Chip Learning with a Scalable Single-Transistor-based Neuromorphic Platform

Abstract Spiking neural networks (SNNs) offer a promising paradigm for energy-efficient computing, yet enabling on-chip training in analog hardware platforms remains challenging because internal neuronal states are difficult to access. Here, we present a hardware–algorithm co-designed neuromorphic architecture for state-access-free learning using the accessible signals of a single-transistor (1T) platform. Current-based surrogate gradient (cSG) and eligible leaky integrate-and-fire encoder (eLIFE) modules generate learning signals from spike events without explicit membrane-potential readout. Co-integrated 1T-synapses, 1T-neurons, and 1T-cSG devices demonstrate synaptic weight storage, leaky integrate-and-fire neuronal dynamics, and surrogate gradient signal generation in a measured unit architecture. At the algorithmic level, simulations demonstrate competitive performance using small-scale networks on F-MNIST, S-MNIST, and SHD and large-scale networks on CIFAR-10, CIFAR-100, CIFAR10DVS, DVS128Gesture, ImageNet, and COCO. Furthermore, hardware-aware simulations of an analog on-chip continual-learning framework demonstrate learning of previously unseen classes with limited average accuracy loss on previously learned classes. Under the adopted model, estimated inference energy is more than 60\% lower than that of fully digital SNN baselines. These results provide a unified device–algorithm framework for state-access-free learning in adaptive neuromorphic systems.