FPGA Implementation of Efficient Polar Encoder and Decoder Architecture for 5G Wireless Communication

Polar codes are error correcting codes used in channel coding to maintain the reliability of transmitted information. They are adopted as the channel code for the control channel in 5G New Radio. Conventional polar codes commonly use a 2x2 binary kernel, which restricts the code length to powers of two. This work presents an FPGA-oriented architecture combining a folded polar encoder with a semi-parallel multi-kernel polar decoder to support more flexible code lengths and rates. The encoder reuses a limited set of functional units over scheduled clock cycles and incorporates puncturing and shortening. The decoder combines binary and ternary processing elements and corresponding combinational blocks, together with Channel LLR RAM, Internal LLR RAM, internal beta RAM, Codeword RAM, Frozen Pattern RAM, LLR bypass registers, beta bypass registers, and dedicated memory interfaces. The decoder data path is further modified so that addition and subtraction results associated with the g operation are stored in separate RAMs, enabling two decoded bits to be produced per clock pulse in the demonstrated schedule. Functional simulations are performed for the binary and mixed processing elements and combinational blocks, and the architecture is synthesized using Xilinx Vivado. Timing and resource-utilization results are reported for Virtex-6 and ZCU102 FPGA configurations. The work provides an implementation-oriented architecture for flexible multi-kernel polar coding and identifies further scope for list decoding, hybrid kernels, and ASIC optimization.