Ferroelectric Hybrid Processor Family - Tier-1 Engineering Specification (HTML)

This document provides the complete engineering specification for the three Tier-1 products of the Ferroelectric Hybrid Processor Family: a standard premium phone chip (Ph-1), a high-end desktop chip (Pc-1), and an entry-level single-socket server chip (Dc-1S). The architecture combines an RV64GCVH out-of-order CPU core, a FeFET non-volatile L3 cache, and an analog AI crossbar on a standard N5 CMOS process with a hafnium zirconium oxide (HfZrO, HZO) back-end module. The document provides the complete engineering parameters for design, fabrication, test, and operation at the specification level: cell geometries, material compositions, fabrication steps, circuit designs, operating procedures, qualification tests, and acceptance criteria (Parts 3--16), plus the register map, firmware interface, interrupt assignments, device tree and ACPI bindings, full pin description, mechanical drawings, bring-up checklist, and security provisioning procedure (Appendices A--H). The advanced optimization promotion is in Part 17. The design is released as a public, patent-free engineering specification.