Fluorine surface engineering for Vt control and memory window boost in HZO FeFET toward high-performance, energy-efficient in-memory computing

Threshold-voltage (V t ) control without sacrificing the memory window remains a key challenge for energy-efficient ferroelectric field-effect transistor (FeFET)-based in-memory computing. Here, we introduce a novel fluorine surface treatment (FST)-based V t tuning strategy that selectively engineers the interfacial layer of Hf 0.5 Zr 0.5 O 2 based Si FeFETs. Fluorine-induced electrostatic modulation and interfacial defect passivation jointly contribute to a positive shift of the entire transfer hysteresis and memory-window enhancement without noticeably altering the ferroelectric switching characteristics of the HZO layer. The optimized FST achieves an approximately 0.5 V positive V t shift, an approximately 0.5 V memory window enhancement, and a 40× reduction in leakage current at 0 V, enabling normally-off operation of the low-V t state. The resulting devices exhibit robust reliability, consistent device-to-device characteristics, and favorable analog synaptic behavior. Furthermore, simulation using the experimentally measured device characteristics improves CIFAR-10 classification accuracy from approximately 78% to 83%. These results establish interfacial-layer-selective fluorine engineering as a compelling route toward low-leakage, reliable, and energy-efficient FeFET-based analog in-memory computing.