Hardware-aware CNN optimization for resource-efficient image classification on FPGA-constrained platforms

Deploying convolutional neural networks (CNNs) on resource-constrained field-programmable gate arrays (FPGAs) remains challenging because hardware cost is often driven not only by parameter count or numerical precision, but also by intermediate activation size and architectural structure. This paper presents a hardware–aware CNN optimization study for image classification on the ZedBoard platform using a Keras—hls4ml—Vivado workflow. A baseline CNN is compared with post–training quantization, quantization–aware training, structured pruning, and activation–aware architectural redesign under the same evaluation framework. The results show that quantization alone provides limited hardware benefit, while structured pruning reduces resource utilization but remains insufficient to satisfy all ZedBoard constraints. In contrast, the final activation- -aware architecture is the first feasible design among the investigated branches. At the HLS synthesis level, it achieves 93.03% test accuracy with 183 BRAM_18K, 201 DSP48E, 40859 FF, 44079 LUT, and 20611 latency cycles. The final accelerator is then implemented in Vivado and physically validated on the ZedBoard. The post–route design uses 34505 LUTs, 35979 FFs, 158 BRAM_18K, and 177 DSP48E1, meets timing at 50 MHz with WNS = +1.547 ns, and achieves 92.97% hardware accuracy on the complete 10000–image MNIST test set with zero execution timeouts and zero BRAM access failures. These results demonstrate that activation-aware topology redesign is an effective strategy for achieving deployable CNN inference on constrained FPGA platforms.