New Insights into the oxidation kinetics of SiGe-on-insulator layers

Fully depleted SiGe-on-insulator (SGOI) structures are promising candidates for next-generation high-performance CMOS technologies where strain engineering is employed to boost carrier mobility, with tensile strain for nMOS and compressive strain for pMOS transistors. However, both their fabrication routes and the underlying physical mechanisms are not yet as well established as in standard Si processing. In this work, we investigate the dry thermal oxidation of thin SGOI layers containing 5%, 15%, and 22% Ge at temperatures of 765, 805, and 895 °C, using pure Si as an experimental reference. Ellipsometry, cross-sectional STEM, STEM-EDX, and geometrical phase analysis reveal the relationships between oxidation kinetics, Ge redistribution, and local lattice deformation. Over the investigated oxide-thickness range of approximately 10–30 nm, the kinetics are consistent with the parabolic regime of the Deal–Grove model. Arrhenius analysis yields oxidation activation energies of approximately 2.00 eV for Si, 1.96 eV for SGOI containing 5% Ge, and 1.82–1.83 eV for layers containing 15% and 22% Ge. The lower activation energies in Ge-richer SGOI are accompanied by pronounced interfacial Ge enrichment and an oxygen signal extending throughout the remaining SiGe layer. These observations suggest that Ge redistribution and oxygen incorporation may jointly modify the conditions for Si transport and oxidation within the oxide/SiGe/oxide architecture.