Materials-Architecture Co-Design of 3D Integrated Circuits: Resolving the Dielectric Thermal Choke and Eliminating TSV Shear via Atomically Ordered B₅C₆N₅ Superlattices and Uncompromised PG(3, q) Routing

## Abstract Three-dimensional integrated circuits (3D-ICs) for high-density AI tensor acceleration face a fundamental physical bottleneck: conventional inter-die bonding oxides ($\mathrm{SiO}_2$, $k_{\mathrm{ox}} = 1.40\,\mathrm{W/(m\cdot K)}$) and carbon-doped silicon nitrides ($\mathrm{SiCN}$, $k = 2.20\,\mathrm{W/(m\cdot K)}$) act as planar thermal blankets between stacked active tiers. In prior projective geometric 3D-IC architectures (*S3P17*), overcoming this dielectric thermal choke required drilling continuous, macro-scale copper Through-Silicon Vias (TSVs, $k_{\mathrm{Cu}} = 385\,\mathrm{W/(m\cdot K)}$) across active silicon substrates and sacrificing $k - \lambda$ channels per node of the finite projective geometry $PG(3, q)$ to serve as vertical thermal chimneys. However, macro-TSVs induce $305.59\,\mathrm{MPa}$ of Lamé thermoelastic shear stress upon cool-down from back-end-of-line (BEOL) bonding ($523.15\,\mathrm{K} \to 300.0\,\mathrm{K}$), enforcing $8.28\,\mu\mathrm{m}$ transistor Keep-Out Zones (KOZs) that forfeit $215.41\,\mu\mathrm{m}^2$ of active CMOS area per via. Here we introduce a closed-loop **Materials-Architecture Co-Design** framework structured across a two-horizon foundry roadmap: (1) **Horizon 1 (Industrial Bridge)**, pairing atomic-layer-deposited $\mathrm{AlN}$ lateral heat spreaders with low-$\kappa$ $\mathrm{SiOC}$ signal-pad collars ($k_\parallel = 162.00\,\mathrm{W/(m\cdot K)}$, $\kappa_{\mathrm{eff}} = 3.20$); and (2) **Horizon 2 (First-Principles Target)**, synthesizing an **atomically ordered zincblende-derived $\mathrm{B_5 C_6 N_5}$ superlattice** ($(\mathrm{BN})_{0.625}(\mathrm{C}_2)_{0.375}$, $98.74\%\,sp^3$ hybridization with $1.26\%$ compliant insulating $sp^2\text{-BN}$ grain boundaries). By preserving translational crystal symmetry ($\eta_{\mathrm{order}} = 0.9992$), the ordered supercell suppresses Klemens $\omega^4$ point-defect phonon scattering, achieving $k_\parallel = 186.38\text{--}210.57\,\mathrm{W/(m\cdot K)}$ ($23.78\times\text{--}26.18\times$ above disordered IBAD $\mathrm{BCN}$ alloys) and a Kapitza-coupled cross-plane effective conductivity of $k_{\perp,\mathrm{eff}} = 116.97\,\mathrm{W/(m\cdot K)}$ across a $1.0\,\mu\mathrm{m}$ isolation stack ($84.60\times$ above $\mathrm{SiO}_2$). Simultaneously, matching the integrated thermal strain of silicon across the entire BEOL bonding envelope ($\int_{300\,\mathrm{K}}^{523.15\,\mathrm{K}} [\alpha_{\mathrm{BCN}}(T) - \alpha_{\mathrm{Si}}(T)]\,dT = 0.00\,\mathrm{ppm}$) collapses residual film stress to $\le 2.00\,\mathrm{MPa}$ under $\pm 0.05\%$ stoichiometric fab tolerances ($99.34\%$ reduction vs. $\mathrm{Cu}$ TSVs). Coupled with pulsed ALD/PECVD growth, chemical-mechanical planarization ($R_a = 0.10\,\mathrm{nm}$), and $\mathrm{O_2/H_2O}$ plasma $\mathrm{B\text{-}OH}$ hydrophilic activation, macro-TSVs are eliminated entirely in favor of BEOL-confined sub-micron direct $\mathrm{Cu\text{-}Cu}$ hybrid bond pads ($0.00\,\mu\mathrm{m}$ active silicon KOZ). In 24,000-cell anisotropic 3D Finite-Volume simulations at $225\,\mathrm{W/cm^2}$, peak die temperature drops from $104.68^\circ\mathrm{C}$ (clustered baseline) and $82.32^\circ\mathrm{C}$ (*S3P17*) to **$61.19^\circ\mathrm{C}$**, with vertical inter-tier thermal differentials collapsing from $23.78^\circ\mathrm{C}$ to **$1.34^\circ\mathrm{C}$**—liberating $100\%$ of $PG(3, q)$ projective lines for non-blocking AllReduce tensor communication ($2.333\times$ to $8.111\times$ bandwidth gain).