Significance-Weighted Tolerance Allocation for Binary-Weighted Measurement Systems Built from Discrete Components: A Closed-Form Rule and Its Validity Boundary
Binary-weighted measurement systems, such as successive-approximation converters built from discrete resistors, sets of reference weights or banks of binary thresholds, are usually specified with one tolerance class for all elements. Because an element's contribution to the conversion error scales with its binary weight, this over-buys precision for the less significant elements. This paper treats per-element tolerance as a cost-constrained allocation problem. For a power-law cost, in which price scales as t−α with tolerance t, the error-variance-optimal allocation is ti ∝ Wi−2/(α+2), and the cost ratio to a uniform design of equal error variance, obtained in closed form, falls approximately as 1/N with the number of bits N. Monte Carlo simulation of a 10-bit converter confirms the closed form (cost ratios of 0.379 for α = 1 and 0.299 for α = 2 at equal RMSE). Because linearity yield is not a variance criterion, tolerance classes are also selected under a yield constraint and validated on 3000 independent units: at ≥ 99 % yield (|INL|, |DNL| ≤ 0.5 LSB) the allocated designs cost 48–74 % less than the cheapest uniform design for α = 0.5 to 2, and 64–67 % less with the catalogue prices of 120 commercial resistors (fitted α ≈ 1.2). SPICE Monte Carlo of a SKY130 capacitor array shows that integrated unit-cell arrays already realise the α = 2 optimum under area-only mismatch; a layout-level study shows that coarser cells for the significant bits help at equal area only when edge mismatch is significant and gradients are moderate.
Authors
- Mohsen Karimi (ORCID: https://orcid.org/0009-0004-1055-8267)
Publication Details
- Journal
- Preprints.org
- Published
- 2026-11-02
- DOI
- https://doi.org/10.20944/preprints202611.0113.v1
- Primary Topic
- Analog and Mixed-Signal Circuit Design
- Type
- preprint