LUPIN: A LUT-Based DRAM-PIM Accelerator for Feature Aggregation in Graph Neural Networks

Processing-in-memory (PIM) architectures have emerged as promising alternatives to conventional von Neumann architectures for accelerating memory-bound applications, such as Graph Neural Networks (GNNs), by reducing data movement between memory and processing units, thereby improving energy efficiency and reducing computational latency. Feature aggregation is a fundamental operation in GNNs; however, the sparsity of graph data leads to poor spatial and temporal locality. This results in dynamic and irregular memory access patterns, ultimately limiting performance and increasing latency. To address this issue, we propose LUPIN, a look-up table (LUT)-based PIM architecture to accelerate GNNs. In this design, logic-based processing is replaced with precalculated results stored in LUTs to perform the required computations within the DRAM memory platform. The proposed LUPIN architecture achieves enhanced performance and markedly improved energy efficiency compared to conventional bitwise-parallel PIM designs. Moreover, it avoids the fabrication challenges associated with integrating logic circuits into memory. It leverages the extensive internal parallelism of DRAM to accelerate the execution of GNN models while maintaining high energy efficiency. Our results demonstrate that LUPIN achieves geometric-mean energy improvements of 32× and 51× on GCN and GIN, respectively, over the CPU and 15× and 19.5×, respectively, over the GPU. Moreover, LUPIN reduces latency by 35.8× and 25.7× on GCN and GIN, respectively, compared with the CPU and 29.6× and 20.5×, respectively, compared with the GPU. The proposed LUPIN architecture achieves nearly 10× higher energy efficiency and 5× speedup compared with the state-of-the-art PIM architectures.