Modeling and Analysis of Reliability Challenges in Nanoscale Transistors

To meet the speed, complexity, circuit density, power consumption, and ultimately cost requirements of many advanced applications, scientists have spent decades shrinking device feature sizes for better performance of metal-oxide semiconductor (MOS) technology. However, there are several disadvantages to switching to these nano size MOS devices. Most of the functional failure in nano-scale devices is caused by aging related phenomena such as negative bias temperature instability (NBTI), hot carrier degradation (HCD), and time dependent dielectric breakdown (TDDB). However, Silicon devices’ dimensions and material capabilities are beginning to hit their limitations. Scientists and researchers have figured out how to replace the current silicon material with an emerging novel material like carbon nano tube. The goal of this research was to develop a drain current and threshold voltage model for carbon nanotube field effect transistors (CNTFETs) that can be used in the analysis and design of reliable integrated circuits, focusing on the reliability issues of conventional metal oxide semiconductor field-effect transistors (MOSFETs) at the nanoscale. To develop this model, we investigated the atomic structure of carbon nanotubes and used the fundamentals of electrostatics to describe a field-effect transistor. By analyzing and defining the electronic structure of carbon nanotubes, we first arrived at analytical formulas for the carrier concentration in carbon nanotubes for various chiral vectors (n, m). By combining several chiral vectors, it is possible to determine the threshold voltage expression that is obtained throughout the procedure as well as the I-V characteristics for CNTFETs. The diameter and chiral angle of carbon nanotubes were shown to be significant determinants of the I-V characteristics and threshold voltage. In terms of the threshold voltage change CNTFET shows better performance 24% less than the conventional MOSFET in 45nm technology node.

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Publication Details

Journal
Saudi Journal of Engineering and Technology
Published
2026-11-02
DOI
https://doi.org/10.36348/sjet.2026.v11i11.002
Primary Topic
Advancements in Semiconductor Devices and Circuit Design
Type
article
Field-Weighted Citation Impact
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article

Modeling and Analysis of Reliability Challenges in Nanoscale Transistors

Md Sadikur Rahman, Md Nasir Uddin
Saudi Journal of Engineering and Technology
Advancements in Semiconductor Devices and Circuit Design
article

Modeling and Analysis of Reliability Challenges in Nanoscale Transistors

Md Sadikur Rahman, Md Nasir Uddin
article en

Abstract

To meet the speed, complexity, circuit density, power consumption, and ultimately cost requirements of many advanced applications, scientists have spent decades shrinking device feature sizes for better performance of metal-oxide semiconductor (MOS) technology. However, there are several disadvantages to switching to these nano size MOS devices. Most of the functional failure in nano-scale devices is caused by aging related phenomena such as negative bias temperature instability (NBTI), hot carrier degradation (HCD), and time dependent dielectric breakdown (TDDB). However, Silicon devices’ dimensions and material capabilities are beginning to hit their limitations. Scientists and researchers have figured out how to replace the current silicon material with an emerging novel material like carbon nano tube. The goal of this research was to develop a drain current and threshold voltage model for carbon nanotube field effect transistors (CNTFETs) that can be used in the analysis and design of reliable integrated circuits, focusing on the reliability issues of conventional metal oxide semiconductor field-effect transistors (MOSFETs) at the nanoscale. To develop this model, we investigated the atomic structure of carbon nanotubes and used the fundamentals of electrostatics to describe a field-effect transistor. By analyzing and defining the electronic structure of carbon nanotubes, we first arrived at analytical formulas for the carrier concentration in carbon nanotubes for various chiral vectors (n, m). By combining several chiral vectors, it is possible to determine the threshold voltage expression that is obtained throughout the procedure as well as the I-V characteristics for CNTFETs. The diameter and chiral angle of carbon nanotubes were shown to be significant determinants of the I-V characteristics and threshold voltage. In terms of the threshold voltage change CNTFET shows better performance 24% less than the conventional MOSFET in 45nm technology node.

Saudi Journal of Engineering and TechnologyVol. 11(11)
Openalex Percentile: Top 25%
Advancements in Semiconductor Devices and Circuit Design
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