Design and Synthesis of an Energy-Efficient Sparsity-Aware 32-Bit Pipelined RISC-V SoC with Integrated CNN Accelerator

This project focuses on designing and implementing a high-performance PQC coprocessor using Verilog HDL and 90 nm CMOS technology. The design is verified and analysed using Cadence EDA tools for functionality, power, area and timing performance.

Authors

Publication Details

Journal
Zenodo (CERN European Organization for Nuclear Research)
Published
2026-11-02
DOI
https://doi.org/10.5281/zenodo.23881173
Primary Topic
Embedded Systems Design Techniques
Type
article
Field-Weighted Citation Impact
0.00
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article

Design and Synthesis of an Energy-Efficient Sparsity-Aware 32-Bit Pipelined RISC-V SoC with Integrated CNN Accelerator

S Shanmathi, Prema C, M MANOVA
Zenodo (CERN European Organization for Nuclear Research)
Embedded Systems Design Techniques
article

Design and Synthesis of an Energy-Efficient Sparsity-Aware 32-Bit Pipelined RISC-V SoC with Integrated CNN Accelerator

S Shanmathi, Prema C, M MANOVA
article en

Abstract

This project focuses on designing and implementing a high-performance PQC coprocessor using Verilog HDL and 90 nm CMOS technology. The design is verified and analysed using Cadence EDA tools for functionality, power, area and timing performance.

Zenodo (CERN European Organization for Nuclear Research)
Industry, innovation and infrastructure
Openalex Percentile: Top 11%
Embedded Systems Design Techniques
DOIOpen Access PDFOpenAlex
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Design and Synthesis of an Energy-Efficient Sparsity-Aware 32-Bit Pipelined RISC-V SoC with Integrated CNN Accelerator — S Shanmathi, Prema C, et al. · Zenodo (CERN European Organization for Nuclear Research) (2026) | TGRS Research Map | TGRS