Fractional-order chaos–driven multi-stage image encryption scheme with an FPGA realization

Abstract The rapid growth of image-centric applications in cloud, IoT/edge, and wireless multimedia systems has intensified the need for encryption schemes that simultaneously deliver strong security and practical real-time implementations. This manuscript proposes a software-hardware co-design of a fractional-order chaos-driven, multiple-layer image encryption pipeline that merges multiple color images, converts them to a $$1\textrm{D}$$ bitstream, and applies consecutive XOR–substitution stages powered by independent fractional-order hyperchaotic generators: a $$5\textrm{D}$$ fractional-order memristive hyperchaotic system, an $$8\textrm{D}$$ fractional-order Chen hyperchaotic system, and a $$10\textrm{D}$$ fractional-order Chen hyperchaotic system, with dynamic S-boxes generated per layer. On standard $$256\times 256$$ test images (USC-SIPI), the scheme achieves near-ideal randomness and diffusion with average encrypted image entropy $$H_E=7.99855$$ , very low post-encryption adjacent-pixel correlations (near zero), and strong differential resistance with NPCR and UACI values very close to their ideal targets; encryption distortion metrics further indicate effective concealment (average PSNR $$=8.06821~\textrm{dB}$$ , MAE $$=82.3120$$ , MSE $$=10146.0$$ ), while decryption is lossless (SSIM $$=1$$ for all reported images). The generated S-boxes exhibit competitive cryptographic properties (NL $$=106$$ –110, SAC $$\approx 0.493$$ –0.505, BIC $$=104$$ –108, DAP $$=0.015625$$ ), the key-stream passes NIST SP 800–22 with all p -values $$>0.01$$ , and the estimated key space is $$2^{2604}$$ . Efficiency is demonstrated in software ( $$0.0482414~\textrm{s}$$ for $$256\times 256$$ ; $$1.33031~\textrm{s}$$ for $$1024\times 1024$$ ) and via an FPGA-oriented architecture on an Artix-7 (XC7A35T) achieving $$78.64~\textrm{Mbps}$$ throughput with $$0.021798~\textrm{s}$$ execution time and minimal resource utilization ( $$\sim 1\%$$ LUT, $$0\%$$ BRAM/DSP), supporting embedded real-time cryptography.