Fault-Tolerant Self-Recovering Finite State Machine (FSM)

The Fault-Tolerant Self-Recovering Finite State Machine (FSM) is a digital system designed to improve the reliability and safety of sequential circuits by detecting and recovering from unexpected state errors. Conventional FSMs may enter invalid states due to hardware faults, electrical disturbances, or transient errors, which can affect system operation. This project proposes a fault-tolerant FSM using Verilog HDL that continuously monitors its internal state and detects invalid state transitions. When an unexpected or illegal state is detected, the system automatically recovers by returning to a predefined safe state without requiring manual intervention. The design includes state monitoring, fault detection, recovery logic, and reset control. The proposed architecture is implemented and verified using Verilog HDL through ModelSim simulation. Xilinx Vivado is used for synthesis and hardware resource analysis. The project aims to improve circuit reliability, fault recovery, and operational stability in FPGA-based digital systems.