ASIC-based design space exploration of precision-scalable multiplier architectures for edge AI accelerators

Deep Neural Networks (DNN) offer greater accuracy in artificial intelligence applications at the cost of increased computational complexity and substantial memory requirements. The traditional resource-rich cloud platform suffers from privacy and latency concerns, necessitating the shift of the computing paradigm from cloud to edge. As the majority of computations in DNN are multiply-and-add operations, realizing DNN hardware on edge devices requires energy-efficient multiplier architectures. According to the algorithmic properties of DNN, the operand bit width can be varied across different neural networks or across layers within the same neural network to improve energy efficiency without significant loss of accuracy. Precision-scalability is a promising approach to reducing computational workload and memory footprint, leading to two dominant computing paradigms: coarse-grained and fine-grained precision-scalable designs, each offering distinct trade-offs in computational flexibility, hardware complexity, and implementation cost. This article presents an ASIC-based design space exploration of precision-scalable multiplier architectures for edge accelerators. Representative fine-grained and coarse-grained architectures are modeled in Verilog hardware description language and synthesized using Cadence® Genus with TSMC 65 nm CMOS technology. The architectures are evaluated in terms of the hardware metrics area, power, delay. In addition to that, the composite metrics area-delay product (ADP) and power-delay product (PDP) are also analyzed to provide a comprehensive assessment of design trade-offs. The presented analysis highlights the trade-offs among the precision-scalable multiplier architectures, providing useful insights for selecting suitable energy-efficient multipliers for edge AI applications.