Traffic Light Controller Using FSM in Verilog HDL

Traffic Light Controller Using Finite State Machine (FSM) is a software-based VLSI project developed using Verilog Hardware Description Language (HDL). The main objective of this project is to design and simulate an automatic traffic light control system that operates in a predefined sequence. The system consists of three traffic signals: Red, Green, and Yellow, which represent STOP, GO, and CAUTION, respectively.A Finite State Machine (FSM) is used to control the transitions between these three states. The controller operates based on clock and reset signals, ensuring proper and systematic switching of traffic lights. Verilog HDL is used to describe the digital circuit, while a testbench is developed to verify its functionality through simulation. The project can be implemented and tested using software tools such as EDA Playground, ModelSim, or Icarus Verilog, along with GTKWave for waveform analysis.