Design and Implementation of a Transformer Attention Accelerator for Edge AI using the Synopsys ASIC Flow

Abstract This work presents the design and implementation of a Transformer Attention Accelerator for Edge AI applications using Verilog HDL and the Synopsys ASIC design flow. The proposed architecture focuses on accelerating key operations involved in the self-attention mechanism, including attention score computation, scaling, Softmax approximation, and weighted-sum generation. The design is developed at the Register Transfer Level (RTL) using a modular architecture. Functional verification is performed using Synopsys VCS, with FSDB waveform analysis through Synopsys Verdi. Logic synthesis is carried out using Synopsys Design Compiler with the SAED 32 nm standard-cell library. The physical implementation methodology uses Synopsys IC Compiler II, covering floorplanning, placement, clock tree synthesis, and routing. The implementation is evaluated in terms of area, timing, and power consumption. The synthesis results and physical design observations are used to study the trade-offs involved in implementing attention-based hardware for resource-constrained Edge AI systems. Keywords: Transformer Accelerator, Self-Attention, Edge AI, Verilog HDL, ASIC Design Flow, VLSI.