An Area-Efficient AXI4-Lite SRAM Controller With SECDED Protection

Memory controllers in safety-critical System-on-Chip (SoC) platforms must stay dependable even when stored bits are disturbed by radiation or electrical noise.This paper describes the design and functional verification of a soft-errorresilient SRAM controller that exposes an AMBA AXI4-Lite slave port.Where earlier parameterizable controllers concentrate on flexibility and burst throughput, the present design adds a Single Error Correction, Double Error Detection (SECDED) block based on the Hamming code, so that a corrupted word can be repaired before it reaches the bus master.The controller is written in SystemVerilog and exercised with a Universal Verification Methodology (UVM) testbench whose randomized fault-injection sequence flips memory bits on demand.Synthesis and implementation in Vivado for the Xilinx Zynq-7000 device (xc7z020) report 188 slice LUTs, 120 slice registers and 0.117 W of total on-chip power.Compared with a reference AXI4-Full reconfigurable controller (395 LUTs, 1.395 W), this is about 52% fewer LUTs and a 91.6% lower reported power figure.Simulation shows that every injected single-bit error is corrected and that double-bit errors raise an error flag, which makes the controller a suitable memory IP block for automotive and other safety-critical SoCs.