Design and Simulation of Serial Communication Between a Microprocessor Training Kit and a PC Using the 8251 USART

Serial communication is the basic method for connecting microprocessor systems to personal computers and peripherals. This paper presents the design of serial communication between a microprocessor training kit and a PC using the Intel 8251 USART. The device is initialized for asynchronous operation, the baud rate is derived from a timer, and RS-232 level conversion connects the kit to the PC terminal. Data integrity at several baud rates and the error flags of the USART are evaluated by calculation and simulation. In simulation the character error rate stayed below 0.01 % up to 19200 baud, the timer-derived baud rates deviated by -2.34 to +0.16 %, and one-bit parity errors were detected in 100 % of cases.

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Publication Details

Journal
Zenodo (CERN European Organization for Nuclear Research)
Published
2026-10-31
DOI
https://doi.org/10.5281/zenodo.23835193
Primary Topic
Embedded Systems and FPGA Applications
Type
preprint
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Design and Simulation of Serial Communication Between a Microprocessor Training Kit and a PC Using the 8251 USART

Yslam Orazov, Kemal Ataýew, Ayjemal Ussayeva
Zenodo (CERN European Organization for Nuclear Research)
Embedded Systems and FPGA Applications
preprint

Design and Simulation of Serial Communication Between a Microprocessor Training Kit and a PC Using the 8251 USART

Yslam Orazov, Kemal Ataýew, Ayjemal Ussayeva
preprint en

Abstract

Serial communication is the basic method for connecting microprocessor systems to personal computers and peripherals. This paper presents the design of serial communication between a microprocessor training kit and a PC using the Intel 8251 USART. The device is initialized for asynchronous operation, the baud rate is derived from a timer, and RS-232 level conversion connects the kit to the PC terminal. Data integrity at several baud rates and the error flags of the USART are evaluated by calculation and simulation. In simulation the character error rate stayed below 0.01 % up to 19200 baud, the timer-derived baud rates deviated by -2.34 to +0.16 %, and one-bit parity errors were detected in 100 % of cases.

Zenodo (CERN European Organization for Nuclear Research)
Oguz Han Engineering and Technology University of Turkmenistan (TM)
Embedded Systems and FPGA Applications
DOIOpen Access PDFOpenAlex
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