Hardware Aligned Training for Perceptron Branch Prediction: An FPGA Based Evaluation of Low Precision Training Strategies

Precision mismatch is a common issue in offline-trained branch predictors. When models are trained in floating-point arithmetic and deployed on low-precision hardware, they lose accuracy. In this work, we study how the training methodology affects the final prediction accuracy of a perceptron-based branch predictor on FPGA. We propose a hardware-aligned training methodology where the model is trained to match the numerical setup of the hardware, including int8 weights, ±1 inputs, and saturation limits. The methodology ensures that post-training quantization is not needed before deployment by reducing the computation to additions and subtractions only. The approach is evaluated on six branch prediction traces covering different workload types. The model achieves 97.1% average prediction accuracy and consistently outperforms the float32 baseline on every trace, while naive post-training quantization degrades accuracy by an average of 7.6 percentage points. It is synthesized on a Zynq-7020 FPGA, showing low resource usage and high throughput, occupying 637 LUTs with zero DSP and zero BRAM usage. Overall, the results suggest that matching the training process with the hardware precision is an important factor in achieving reliable accuracy in low-precision branch prediction.