Color expansion of a 1-bpp frame buffer with a per-tile color lookup table in an MCU DMA engine

A frame buffer of 1 bit per pixel is divided in tiles of 8×8 pixels. Each tile has a 4-bit index into a color lookup table (CLUT) of 16 foreground/background color pairs. A DMA engine in a microcontroller (MCU) reads the bitmap, the tile index map and the CLUT, and produces RGB565, RGB444 or RGB666 pixels on the fly, straight into a serial display interface such as SPI. No color frame buffer exists anywhere. A 240×240 display needs 7.7 kB (7,714 bytes) of RAM instead of 115 kB (115,200 bytes) for a 16-bit frame buffer. The aim is to make color displays usable on microcontrollers that cannot afford a color frame buffer. Changing a CLUT entry recolors every tile that uses it, without redrawing. The engine has two stages with one register between them: a fetch stage that reads memory and an output stage that sends the bytes, so the memory reads of a tile overlap the output of the previous tile. The same expansion in the scan-out path of a display controller is also described. Two anti-aliasing variants are also disclosed: 2 bits per pixel, and two bit planes (section 6). This document is a defensive publication: it discloses the methods described, and the variants listed in section 6, so that they are prior art. The PDF includes a Chinese abstract. The accompanying files (clut-dma.zip; also tag v1.0 of https://github.com/koendv/clut-dma) hold the Verilog model of the engine, its testbench, the formal properties, and an FPGA prototype with a Cortex-M1 soft core and a 240×280 ST7789 display. The software version of the engine is in the u8g2 graphics library, branch clut of https://github.com/koendv/u8g2 (tag clut-dma-v1.0). License: text (clut-dma.pdf) CC BY 4.0; code in clut-dma.zip BSD-2-Clause.