A Near Threshold SRAM Compute-in-Memory Transformer Accelerator with Adaptive Precision Scaling for Sub mW Edge AI Applications

The increasing trend towards the adoption of transformers in edge devices stipulates the need for ultralow power devices that also require high energy efficiency with power budget constraints. This article proposes a near-threshold SRAM compute-in-memory transformer accelerator with adaptive precision scaling for sub-mW edge AI applications. The architecture performs MAC operations directly inside a modified 6T SRAM cell, minimizing data movement between compute and memory. Operating at 0.45 V reduces total power consumption by 58% compared with conventional digital MAC accelerators running at 0.9 V. An adaptive precision precision mechanism has been implemented to switch between the INT4 and INT8 precision dynamically based on the sensitivity of the layer, resulting in an additional 27% savings with less than 1.2% degradation on TinyML transformer benchmarks. The proposed accelerator is implemented in 28 nm CMOS. All reported results (power, energy efficiency, MAC linearity, and noise margins) are obtained from post-layout simulations using TSMC 28 nm LP foundry models and SPEF-extracted parasitics; they are not silicon measurements. The design shows an energy efficiency of 12.4 TOPS/W with a total power of 0.82 mW at 50 MHz.