IP Protection of HLS-based DSP Designs using Parallel Encoding and Multi-Layer Encoded Transformation

Consumer electronic (CE) systems contain several digital signal processing (DSP) designs as intellectual property (IP). However, the IP piracy threat poses a momentous concern for the CE hardware community due to globalization in the design supply chain. This paper presents a novel IP protection technique for high-level synthesis (HLS)-based DSP designs used in CE devices, based on parallel encoding and multilayer encoded transformation logic, to distinguish between pirated and authentic IP versions. The paper also presents a demonstration of the proposed security technique on discrete cosine transformation (DCT) core DSP design. The proposed approach is sturdy against tampering and collision attack, as evident from the lower probability of coincidence (signifying sturdy digital evidence), higher tamper tolerance and enhanced attacker’s effort obtained compared to prior works, at nominal design area overhead. Results of the proposed approach revealed (a) probability of coincidence of upto 1.24E-14, (b) tamper tolerance of 1.34E+154 at nominal design area overhead and minimal implementation runtime. Comparison with several prior works revealed lower probability of coincidence, higher tamper tolerance and greater attacker’s effort, needed by the proposed approach.